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FLEX 6000
(R)
Programmable Logic Device Family
Data Sheet
March 2001, ver. 4.1
%
Typical gates (1) Logic elements (LEs) Maximum I/O pins Supply voltage (V CCINT)
10,000 880 102 3.3 V
16,000 1,320 204 5.0 V
16,000 1,320 171 3.3 V
24,000 1,960 218 3.3 V
Altera Corporation
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FLEX 6000 Programmable Logic Device Family Data Sheet
EPF6010A EPF6016 EPF6016A EPF6024A
71 81 81
102 117 117 117 171 171 171 199 218 199 204 171 219
2
Altera Corporation
FLEX 6000 Programmable Logic Device Family Data Sheet
16-bit loadable counter 16-bit accumulator 24-bit accumulator 16-to-1 multiplexer (pin-to-pin) (1) 16 16 multiplier with a 4-stage pipeline
16 16 24 10 592
172 172 136 12.1 84
153 153 123 13.4 67
133 133 108 16.6 58
MHz MHz MHz ns MHz
Altera Corporation
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FLEX 6000 Programmable Logic Device Family Data Sheet
8-bit, 16-tap parallel finite impulse response (FIR) filter 8-bit, 512-point fast Fourier transform (FFT) function universal asynchronous receiver/transmitter (UART) PCI bus target with zero wait states
599 1,182 487 609
94 75 63 36 56
80 89 53 30 49
72 109 43 25 42
MSPS S MHz MHz MHz
4
Altera Corporation
FLEX 6000 Programmable Logic Device Family Data Sheet
Altera Corporation
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FLEX 6000 Programmable Logic Device Family Data Sheet
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Altera Corporation
FLEX 6000 Programmable Logic Device Family Data Sheet
Altera Corporation
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FLEX 6000 Programmable Logic Device Family Data Sheet
Dedicated Inputs
4
LE 1 LABCTRL1/ SYNCLR LABCTRL2
CLK1/SYNLOAD
CLK2
8
Altera Corporation
FLEX 6000 Programmable Logic Device Family Data Sheet
Carry-In
Cascade-In
data1 data2 data3 data4
Look-Up
Table
(LUT)
Carry Chain
Cascade Chain
D
PRN Q
LE-Out
CLRN
labctrl1 labctrl2 Chip-Wide Reset
Clear/ Preset Logic Clock Select
labctrl3 labctrl4
Carry-Out Cascade-Out
Altera Corporation
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FLEX 6000 Programmable Logic Device Family Data Sheet
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Altera Corporation
FLEX 6000 Programmable Logic Device Family Data Sheet
Carry-In
a1 b1
LUT
Register
s1
Carry Chain LE 2
a2 b2
LUT
Register
s2
Carry Chain LE 3
an bn
LUT
Register
sn
Carry Chain LE n + 1
LUT
Register
Carry-Out
Carry Chain LE n + 2
Altera Corporation
11
FLEX 6000 Programmable Logic Device Family Data Sheet
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Altera Corporation
FLEX 6000 Programmable Logic Device Family Data Sheet
LE 2
LE 2
d[3..0]
LUT
d[3..0]
LUT
LE 3
LE 3
d[7..4]
LUT
d[7..4]
LUT
LE + 1
LE
+1
d[(4 -1)..4( -1)]
LUT
d[(4 -1)..4( -1)]
LUT
Altera Corporation
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FLEX 6000 Programmable Logic Device Family Data Sheet
Carry-In data1 data2 data3 data4 4-Input LUT
Cascade-In LE-Out PRN Q
D
CLRN
Cascade-Out
Carry-In
Cascade-In LE-Out
data1 data2
3-Input LUT
PRN D Q
3-Input LUT Cascade-Out Carry-Out
CLRN
Carry-In
Cascade-In
LAB-Wide Synchronous Load
LAB-Wide Synchronous Clear
data1 data2 data3 (data)
3-Input LUT
D
PRN Q
LE-Out
3-Input LUT Carry-Out Cascade-Out
CLRN
14
Altera Corporation
FLEX 6000 Programmable Logic Device Family Data Sheet
Altera Corporation
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FLEX 6000 Programmable Logic Device Family Data Sheet
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Altera Corporation
FLEX 6000 Programmable Logic Device Family Data Sheet
D
Q
labctrl1 or labctrl2 Chip-Wide Reset PRN Q
CLRN labctrl1 or labctrl2 Chip-Wide Reset
D
Altera Corporation
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FLEX 6000 Programmable Logic Device Family Data Sheet
2 5 22 2 20 5 5 5 5 10 LE 1 through LE 5 LE 6 through LE 10 5 5 10 5
2 22 2 20 5 5 5 10 LE 1 through LE 5 LE 6 through LE 10 5 10
5 To/From Adjacent LAB 10 10
10 10 5 10
5 10 10
10 10 5 10
5 10
10 5 To/From Adjacent LAB
10
10
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Altera Corporation
FLEX 6000 Programmable Logic Device Family Data Sheet
Altera Corporation
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FLEX 6000 Programmable Logic Device Family Data Sheet
LE
LE
From Adjacent Local Interconnect
20
Altera Corporation
FLEX 6000 Programmable Logic Device Family Data Sheet
EPF6010A EPF6016 EPF6016A EPF6024A
4 6 7
144 144 186
22 22 28
20 20 30
Altera Corporation
21
FLEX 6000 Programmable Logic Device Family Data Sheet
4 LAB (Repeated Across Device)
LAB C1
LAB C22
LAB D1
LAB D22
22
Altera Corporation
FLEX 6000 Programmable Logic Device Family Data Sheet
To Row or Column Interconnect
Delay
Chip-Wide Output Enable From LAB Local Interconnect
From LAB Local Interconnect Slew-Rate Control
Altera Corporation
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FLEX 6000 Programmable Logic Device Family Data Sheet
IOE LAB
IOE
24
Altera Corporation
FLEX 6000 Programmable Logic Device Family Data Sheet
IOE
IOE
LAB
Altera Corporation
25
FLEX 6000 Programmable Logic Device Family Data Sheet
Printed Circuit Board Designed for 256-Pin FineLine BGA Package
100-Pin FineLine BGA
256-Pin FineLine BGA
100-Pin FineLine BGA Package (Reduced I/O Count or Logic Requirements)
256-Pin FineLine BGA Package (Increased I/O Count or Logic Requirements)
EPF6016A EPF6024A
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Altera Corporation
FLEX 6000 Programmable Logic Device Family Data Sheet
3.3 3.3 5.0 5.0
2.5 3.3 3.3 5.0 (1)
Altera Corporation
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FLEX 6000 Programmable Logic Device Family Data Sheet
SAMPLE/PRELOAD Allows a snapshot of the signals at the device pins to be captured and examined during normal device operation, and permits an initial data pattern to be output at the device pins. EXTEST BYPASS Allows the external circuitry and board-level interconnections to be tested by forcing a test pattern at the output pins and capturing test result at the input pins. Places the 1-bit bypass register between the and pins, which allows the BST data to pass synchronously through the selected device to adjacent devices during normal device operation.
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Altera Corporation
FLEX 6000 Programmable Logic Device Family Data Sheet
EPF6010A EPF6016 EPF6016A EPF6024A
522 621 522 666
TMS
TDI t JCP t JCH TCK tJPZX TDO tJSSU Signal to Be Captured Signal to Be Driven tJSH t JPCO t JPXZ t JCL t JPSU t JPH
tJSZX
tJSCO
tJSXZ
Altera Corporation
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FLEX 6000 Programmable Logic Device Family Data Sheet
tJCP tJCH tJCL tJPSU tJPH tJPCO tJPZX tJPXZ tJSSU tJSH tJSCO tJSZX tJSXZ
clock period clock high time clock low time JTAG port setup time JTAG port hold time JTAG port clock-to-output JTAG port high impedance to valid output JTAG port valid output to high impedance Capture register setup time Capture register hold time Update register clock-to-output Update register high impedance to valid output Update register valid output to high impedance
100 50 50 20 45 25 25 25 20 45 35 35 35
ns ns ns ns ns ns ns ns ns ns ns ns ns
%
464 (703 [521 Device Output
VCC ) To Test System
250 (8.06 k ) [481 Device input rise and fall times < 3 ns
C1 (includes JIG capacitance)
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Altera Corporation
FLEX 6000 Programmable Logic Device Family Data Sheet
V CC VI I OUT T STG T AMB TJ
Supply voltage DC input voltage DC output current, per pin Storage temperature Ambient temperature Junction temperature
With respect to ground (2)
-2.0 -2.0 -25
7.0 7.0 25 150 135 135
V V mA C C C
No bias Under bias PQFP, TQFP, and BGA packages
-65 -65
V CCINT V CCIO
Supply voltage for internal logic and input buffers
(3), (4)
4.75 (4.50) 4.75 (4.50) 3.00 (3.00) -0.5 0
5.25 (5.50) 5.25 (5.50) 3.60 (3.60) V CCINT + 0.5 V CCIO 85 100 40 40
V V V V V C C ns ns
Supply voltage for output buffers, (3), (4) 5.0-V operation Supply voltage for output buffers, (3), (4) 3.3-V operation
VI VO TJ tR tF
Input voltage Output voltage Operating temperature Input rise time Input fall time For commercial use For industrial use
0 -40
Altera Corporation
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FLEX 6000 Programmable Logic Device Family Data Sheet
V IH V IL V OH
High-level input voltage Low-level input voltage 5.0-V high-level TTL output voltage 3.3-V high-level TTL output voltage 3.3-V high-level CMOS output voltage I OH = -8 mA DC, V CCIO = 4.75 V (7) I OH = -8 mA DC, V CCIO = 3.00 V (7) I OH = -0.1 mA DC, V CCIO = 3.00 V (7) I OL = 8 mA DC, V CCIO = 4.75 V (8) I OL = 8 mA DC, V CCIO = 3.00 V (8) I OL = 0.1 mA DC, V CCIO = 3.00 V (8) V I = V CC or ground (8) V I = ground, no load
2.0 -0.5 2.4 2.4 V CCIO - 0.2
V CCINT + 0.5 0.8
V V V V V
V OL
5.0-V low-level TTL output voltage 3.3-V low-level TTL output voltage 3.3-V low-level CMOS output voltage
0.45 0.45 0.2 -10 -40 0.5 10 40 5
V V V A A mA
II I OZ I CC0
Input pin leakage current V CC supply current (standby)
Tri-stated I/O pin leakage current V O = V CC or ground (8)
C IN CINCLK C OUT
Input capacitance for I/O pin
V IN = 0 V, f = 1.0 MHz
8 12 8
pF pF pF
Input capacitance for dedicated input V IN = 0 V, f = 1.0 MHz Output capacitance V OUT = 0 V, f = 1.0 MHz
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Altera Corporation
FLEX 6000 Programmable Logic Device Family Data Sheet
V CC VI I OUT T STG T AMB TJ
Supply voltage DC input voltage DC output current, per pin Storage temperature Ambient temperature Junction temperature
With respect to ground (2)
-0.5 -2.0 -25
4.6 5.75 25 150 135 135
V V mA C C C
No bias Under bias PQFP, PLCC, and BGA packages
-65 -65
V CCINT V CCIO
Supply voltage for internal logic and (3), (4) input buffers Supply voltage for output buffers, 3.3-V operation Supply voltage for output buffers, 2.5-V operation (3), (4) (3), (4)
3.00 (3.00) 3.00 (3.00) 2.30 (2.30) -0.5 0
3.60 (3.60) 3.60 (3.60) 2.70 (2.70) 5.75 V CCIO 85 100 40 40
V V V V V C C ns ns
VI VO TJ tR tF
Input voltage Output voltage Operating temperature Input rise time Input fall time For commercial use For industrial use
0 -40
Altera Corporation
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FLEX 6000 Programmable Logic Device Family Data Sheet
V IH V IL V OH
High-level input voltage Low-level input voltage 3.3-V high-level TTL output voltage 3.3-V high-level CMOS output voltage 2.5-V high-level output voltage I OH = -8 mA DC, V CCIO = 3.00 V (7) I OH = -0.1 mA DC, V CCIO = 3.00 V (7) I OH = -100 A DC, V CCIO = 2.30 V (7) I OH = -1 mA DC, V CCIO = 2.30 V (7) I OH = -2 mA DC, V CCIO = 2.30 V (7)
1.7 -0.5 2.4 V CCIO - 0.2 2.1 2.0 1.7
5.75 0.8
V V V V V V V
V OL
3.3-V low-level TTL output voltage 3.3-V low-level CMOS output voltage 2.5-V low-level output voltage
I OL = 8 mA DC, V CCIO = 3.00 V (8) I OL = 0.1 mA DC, V CCIO = 3.00 V (8) I OL = 100 A DC, V CCIO = 2.30 V (8) I OL = 1 mA DC, V CCIO = 2.30 V (8) I OL = 2 mA DC, V CCIO = 2.30 V (8)
0.45 0.2 0.2 0.4 0.7 -10 -10 0.5 10 10 5
V V V V V A A mA
II I OZ I CC0
Input pin leakage current V CC supply current (standby)
V I = 5.3 V to ground (8) V I = ground, no load
Tri-stated I/O pin leakage current V O = 5.3 V to ground (8)
C IN CINCLK C OUT
Input capacitance for I/O pin
V IN = 0 V, f = 1.0 MHz
8 12 8
pF pF pF
Input capacitance for dedicated input V IN = 0 V, f = 1.0 MHz Output capacitance V OUT = 0 V, f = 1.0 MHz
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Altera Corporation
FLEX 6000 Programmable Logic Device Family Data Sheet
EPF6010A EPF6016A
100
EPF6010A EPF6016A VCCINT = 3.3 V VCCIO = 3.3 V Room Temperature IOL
100
VCCINT = 3.3 V VCCIO = 2.5 V Room Temperature IOL
75 Typical IO Output Current (mA) 50
75 Typical IO Output Current (mA) 50
IOH
25 25
IOH
1
2
3
4
5
1
2
3
4
5
VO Output Voltage (V) EPF6016
150
VO Output Voltage (V) EPF6016
150
IOL
120 120
IOL VCCINT = 5.0 V VCCIO = 3.3 V Room Temperature
90 Typical IO Output Current (mA) 60
VCCINT = 5.0 V VCCIO = 5.0 V Room Temperature IOH
90 Typical IO Output Current (mA) 60
IOH
30
30
1
2
3
4
5
1
2
3 3.3
4
5
VO Output Voltage (V) EPF6024A
100
VO Output Voltage (V) EPF6024A
75 Typical IO Output Current (mA) 50
VCCINT = 3.3 V VCCIO = 3.3 V Room Temperature IOL
100
75 Typical IO Output Current (mA) 50
VCCINT = 3.3 V VCCIO = 2.5 V Room Temperature IOL
25
25
IOH
1 2 3 4 5 1 2
IOH
3 4 5
VO Output Voltage (V)
VO Output Voltage (V)
Altera Corporation
35
FLEX 6000 Programmable Logic Device Family Data Sheet
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Altera Corporation
FLEX 6000 Programmable Logic Device Family Data Sheet
Carry-In from Previous LE
Cascade-In from Previous LE
LE
Carry-out to Carry-out to Next LE in Next LE in Same LAB Next LAB
Cascade-out Cascade-out to Next LE in to Next LE in Same LAB Next LAB
I/O Pin
IOE
Altera Corporation
37
FLEX 6000 Programmable Logic Device Family Data Sheet
tREG_TO_REG tCASC_TO_REG tCARRY_TO_REG tDATA_TO_REG tCASC_TO_OUT tCARRY_TO_OUT tDATA_TO_OUT tREG_TO_OUT tSU tH tCO tCLR tC tLD_CLR
LUT delay for LE register feedback in carry chain Cascade-in to register delay Carry-in to register delay LE input to register delay Cascade-in to LE output delay Carry-in to LE output delay LE input to LE output delay Register output to LE output delay LE register setup time before clock; LE register recovery time after asynchronous clear LE register hold time after clock LE register clock-to-output delay LE register clear delay LE register control signal delay Synchronous load or clear delay in counter mode
tCARRY_TO_CARRY Carry-in to carry-out delay tREG_TO_CARRY tDATA_TO_CARRY tCARRY_TO_CASC tCASC_TO_CASC tREG_TO_CASC tDATA_TO_CASC tCH tCL Register output to carry-out delay LE input to carry-out delay Carry-in to cascade-out delay Cascade-in to cascade-out delay Register-out to cascade-out delay LE input to cascade-out delay LE register clock high time LE register clock low time
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Altera Corporation
FLEX 6000 Programmable Logic Device Family Data Sheet
tOD1 tOD2 tOD3 tXZ tZX1 tZX2 tZX3 tIOE tIN tIN_DELAY
Output buffer and pad delay, slow slew rate = off, VCCIO = VCCINT Output buffer and pad delay, slow slew rate = off, VCCIO = low voltage Output buffer and pad delay, slow slew rate = on Output buffer disable delay Output buffer enable delay, slow slew rate = off, VCCIO = VCCINT Output buffer enable delay, slow slew rate = off, VCCIO = low voltage IOE output buffer enable delay, slow slew rate = on Output enable control delay Input pad and buffer to FastTrack Interconnect delay Input pad and buffer to FastTrack Interconnect delay with additional delay turned on
C1 = 35 pF (2) C1 = 35 pF (3) C1 = 35 pF (4) C1 = 5 pF C1 = 35 pF (2) C1 = 35 pF (3) C1 = 35 pF (4)
tLOCAL tROW tCOL tDIN_D tDIN_C tLEGLOBAL tLABCARRY tLABCASC
LAB local interconnect delay Row interconnect routing delay Column interconnect routing delay Dedicated input to LE data delay Dedicated input to LE control delay LE output to LE control via internally-generated global signal delay Routing delay for the carry-out of an LE driving the carry-in signal of a different LE in a different LAB Routing delay for the cascade-out signal of an LE driving the cascade-in signal of a different LE in a different LAB (5) (5) (5) (5)
t1 tDRR
Register-to-register test pattern Register-to-register delay via 4 LEs, 3 row interconnects, and 4 local interconnects
(6) (7)
Altera Corporation
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FLEX 6000 Programmable Logic Device Family Data Sheet
tINSU tINH tOUTCO
Setup time with global clock at LE register Hold time with global clock at LE register Clock-to-output delay with global clock with LE register using FastFLEX I/O pin
(8) (8) (8)
% % % %
REG_TO_REG CASC_TO_REG CARRY_TO_REG DATA_TO_REG CASC_TO_OUT CARRY_TO_OUT DATA_TO_OUT REG_TO_OUT SU H
1.2 0.9 0.9 1.1 1.3 1.6 1.7 0.4 0.9 1.4 1.0 1.7
1.3 1.0 1.0 1.2 1.4 1.8 2.0 0.4 1.3 2.1
1.7 1.2 1.2 1.5 1.8 2.3 2.5 0.5
ns ns ns ns ns ns ns ns ns ns
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Altera Corporation
FLEX 6000 Programmable Logic Device Family Data Sheet
CO CLR C LD_CLR CARRY_TO_CARRY REG_TO_CARRY DATA_TO_CARRY CARRY_TO_CASC CASC_TO_CASC REG_TO_CASC DATA_TO_CASC CH CL
0.3 0.4 1.8 1.8 0.1 1.6 2.1 1.0 0.5 1.4 1.1 2.5 2.5 3.0 3.0
0.4 0.4 2.1 2.1 0.1 1.9 2.5 1.1 0.6 1.7 1.2 3.5 3.5
0.4 0.5 2.6 2.6 0.1 2.3 3.0 1.4 0.7 2.1 1.5
ns ns ns ns ns ns ns ns ns ns ns ns ns
OD1 OD2 OD3 XZ XZ1 XZ2 XZ3 IOE IN IN_DELAY
1.9 4.1 5.8 1.4 1.4 3.6 5.3 0.5 3.6 4.8
2.2 4.8 6.8 1.7 1.7 4.3 6.3 0.6 4.1 5.4
2.7 5.8 8.3 2.1 2.1 5.2 7.7 0.7 5.1 6.7
ns ns ns ns ns ns ns ns ns ns
Altera Corporation
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FLEX 6000 Programmable Logic Device Family Data Sheet
LOCAL ROW COL DIN_D DIN_C LEGLOBAL LABCARRY LABCASC
0.7 2.9 1.2 5.4 4.3 2.6 0.7 1.3
0.7 3.2 1.3 5.7 5.0 3.0 0.8 1.4
1.0 3.2 1.4 6.4 6.1 3.7 0.9 1.8
ns ns ns ns ns ns ns ns
t1
EPF6010A EPF6016A
37.6 38.0
43.6 44.0
53.7 54.1
ns ns
tINSU tINH tOUTCO
2.1 (1) 0.2 (2) 2.0 7.1
2.4 (1) 0.3 (2) 2.0 8.2
3.3 (1) 0.1 (2) 2.0 10.1
ns ns ns
42
Altera Corporation
FLEX 6000 Programmable Logic Device Family Data Sheet
tREG_TO_REG tCASC_TO_REG tCARRY_TO_REG tDATA_TO_REG tCASC_TO_OUT tCARRY_TO_OUT tDATA_TO_OUT tREG_TO_OUT tSU tH tCO tCLR tC tLD_CLR tCARRY_TO_CARRY tREG_TO_CARRY tDATA_TO_CARRY tCARRY_TO_CASC tCASC_TO_CASC tREG_TO_CASC tDATA_TO_CASC tCH tCL 4.0 4.0 1.1 1.8
2.2 0.9 1.6 2.4 1.3 2.4 2.7 0.3 1.6 2.3 0.3 0.5 1.2 1.2 0.2 0.8 1.7 1.7 0.9 1.6 1.7 4.0 4.0
2.8 1.2 2.1 3.0 1.7 3.0 3.4 0.5
ns ns ns ns ns ns ns ns ns ns
0.4 0.6 1.5 1.5 0.4 1.1 2.2 2.2 1.2 2.0 2.1
ns ns ns ns ns ns ns ns ns ns ns ns ns
tOD1 tOD2
2.3 4.6
2.8 5.1
ns ns
Altera Corporation
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FLEX 6000 Programmable Logic Device Family Data Sheet
tOD3 tXZ tZX1 tZX2 tZX3 tIOE tIN tIN_DELAY
4.7 2.3 2.3 4.6 4.7 0.5 3.3 4.6
5.2 2.8 2.8 5.1 5.2 0.6 4.0 5.6
ns ns ns ns ns ns ns ns
tLOCAL tROW tCOL tDIN_D tDIN_C tLEGLOBAL tLABCARRY tLABCASC
0.8 2.9 2.3 4.9 4.8 3.1 0.4 0.8
1.0 3.3 2.5 6.0 6.0 3.9 0.5 1.0
ns ns ns ns ns ns ns ns
t1 tDRR
53.0 16.0
65.0 20.0
ns ns
44
Altera Corporation
FLEX 6000 Programmable Logic Device Family Data Sheet
tINSU tINH tOUTCO
3.2 0.0 2.0 7.9
4.1 0.0 2.0 9.9
ns ns ns
tREG_TO_REG tCASC_TO_REG tCARRY_TO_REG tDATA_TO_REG tCASC_TO_OUT tCARRY_TO_OUT tDATA_TO_OUT tREG_TO_OUT tSU tH tCO tCLR tC tLD_CLR tCARRY_TO_CARRY tREG_TO_CARRY tDATA_TO_CARRY tCARRY_TO_CASC tCASC_TO_CASC tREG_TO_CASC tDATA_TO_CASC tCH tCL Altera Corporation 2.5 2.5 0.9 1.3
1.2 0.7 1.6 1.3 1.2 2.0 1.8 0.3 1.0 1.4 0.2 0.3 1.9 1.9 0.2 1.4 1.3 1.1 0.7 1.4 1.0 3.0 3.0
1.3 0.8 1.8 1.4 1.3 2.2 2.1 0.3 1.2 1.7 0.3 0.3 2.1 2.1 0.2 1.6 1.4 1.2 0.8 1.6 1.1 3.5 3.5
1.6 1.0 2.2 1.7 1.6 2.6 2.6 0.4
ns ns ns ns ns ns ns ns ns ns
0.3 0.4 2.5 2.5 0.3 1.9 1.7 1.4 1.0 1.9 1.3
ns ns ns ns ns ns ns ns ns ns ns ns ns 45
FLEX 6000 Programmable Logic Device Family Data Sheet
tOD1 tOD2 tOD3 tXZ tXZ1 tXZ2 tXZ3 tIOE tIN tIN_DELAY
1.9 4.0 7.0 4.3 4.3 6.4 9.4 0.5 3.3 5.3
2.1 4.4 7.8 4.8 4.8 7.1 10.5 0.6 3.7 5.9
2.5 5.3 9.3 5.8 5.8 8.6 12.6 0.7 4.4 7.0
ns ns ns ns ns ns ns ns ns ns
tLOCAL tROW tCOL tDIN_D tDIN_C tLEGLOBAL tLABCARRY tLABCASC
0.8 3.0 3.0 5.4 4.6 3.1 0.6 0.3
0.8 3.1 3.2 5.6 5.1 3.5 0.7 0.3
1.1 3.3 3.4 6.2 6.1 4.3 0.8 0.4
ns ns ns ns ns ns ns ns
45.0
50.0
60.0
ns
46
Altera Corporation
FLEX 6000 Programmable Logic Device Family Data Sheet
tINSU tINH tOUTCO
2.0 (1) 0.2 (2) 2.0 7.4
2.2 (1) 0.2 (2) 2.0 8.2
2.6 (1) 0.3 (2) 2.0 9.9
ns ns ns
---------------------------
EPF6010A EPF6016 EPF6016A EPF6024A Altera Corporation
14 88 14 14 47
FLEX 6000 Programmable Logic Device Family Data Sheet
48
Altera Corporation
FLEX 6000 Programmable Logic Device Family Data Sheet
1000 200 800 150
ICC Supply Current 100 (mA)
50
ICC Supply Current (mA)
600
400
200
0
50
100
0
30
60
Frequency (MHz)
Frequency (MHz)
250
400
200 300
ICC Supply 150 Current (mA)
100
ICC Supply Current (mA)
200
50
100
0
50
100
0
50
100
Frequency (MHz)
Frequency (MHz)
Altera Corporation
49
FLEX 6000 Programmable Logic Device Family Data Sheet
Configuration device Passive serial (PS)
EPC1 or EPC1441 configuration device BitBlaster TM, ByteBlasterMVTM, or MasterBlaster TM download cables, or serial data source
Passive serial asynchronous BitBlaster, ByteBlasterMV, or MasterBlaster (PSA) download cables, or serial data source
50
Altera Corporation
FLEX 6000 Programmable Logic Device Family Data Sheet
Altera Corporation
51
FLEX 6000 Programmable Logic Device Family Data Sheet
(R)
52
Printed on Recycled Paper.
Altera Corporation

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